Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a circuit for generating an internal voltage of a semiconductor device.
Typical semiconductor devices including DRAM can include an internal voltage generator provided in a chip. The internal voltage generator is configured to generate a plurality of internal voltages having a variety of voltage levels. The internal voltage generator may use a power supply voltage VDD and a ground voltage VSS, which are supplied from outside the chip. The internal voltage generator supplies a plurality of interval voltages for the operations of an internal circuit of the chip.
Such internal voltages can include VBLP, VCP, VPP, and VCORE depending on the purpose. VBLP is a bit line precharge voltage, VCP is a cell plate voltage, VPP is a voltage for enabling a word line, and VCORE is a voltage for inputting the high data of a cell.
FIG. 1 is a block diagram illustrating a circuit for controlling a core voltage driver in a conventional memory device.
Referring to FIG. 1, the circuit for controlling a core voltage driver in the conventional memory device including a plurality of banks 30 to 37 includes a bank selection driving control signal generation unit 10, a driving control signal generation unit 50, and a core voltage driver 20. The bank selection driving control signal generation unit 10 is configured to generate a plurality of bank selection driving control signals RACTV<0:1>, RACTV<2:3>, RACTV<4:5>, and RACTV<6:7> corresponding to the plurality of banks 30 to 37 in response to an active command signal ACT_CMD and an address signal ADDRESS. The driving control signal generation unit 50 is configured to generate a driving control signal YBST in response to a read control signal CASP10RD corresponding to a read command signal READ_CMD and write control signals CASP10WTB4 and CASP10WTB8 corresponding to a wire command signal WRITE_CMD. The core voltage driver 20 is configured to selectively drive core voltage terminals corresponding to the plurality of banks 30 to 37 in response to the plurality of bank selection driving control signals RACTV<0:1>, RACTV<2:3>, RACTV<4:5>, and RACTV<6:7> and the driving control signal YBST.
Furthermore, the circuit for controlling a core voltage driver 20 includes a column selection control signal generation unit 40 that is configured to generate column selection control signals CASPBK<0:7> for selecting any one of banks 30 to 37, in which a column selection operation is to be performed, in response to the read control signal CASP10RD corresponding to the read command signal READ_CMD, in response to either one of the write control signals CASP10WTB4 and CASP10WTB8 corresponding to the write command signal WRITE_CMD, and in response to either of the bank selection control signals BANK<0:2> corresponding to the address signal ADDRESS.
The core voltage driver 20 selectively drives the core voltage terminals corresponding to the plurality of banks 30 to 37 in response to a plurality of driving control pulses ENPULSE01, ENPULSE23, ENPULSE45, and ENPULSE67, where the plurality of driving control pulses ENPULSE01, ENPULSE23, ENPULSE45, and ENPULSE67 are selectively toggled in response to activation of any one of the corresponding pair of bank selection driving signals of the plurality of bank selection driving control signals RACTV<0:1>, RACTV<2:3>, RACTV<4:5>, and RACTV<6:7>.
On the other hand, when the driving control signal YBST is activated, the core voltage driver 20 selectively drives the core voltage terminals corresponding to the plurality of banks 30 to 37 by toggling only a driving control pulse ENPULSE01, ENPULSE23, ENPULSE45, or ENPULSE67 corresponding to an activated bank selection driving control signal RACTV<0>, RACTV<1>, RACTV<2>, RACTV<3>, RACTV<4>, RACTV<5>, RACTV<6>, or RACTV<7> during the activation period.
That is, the selection of a core voltage terminal which is to be driven, from among the core voltage terminals corresponding to the plurality of banks 30 to 37, is determined depending on which signal is activated among the plurality of bank selection driving control signals RACTV<0> to RACTV<7>.
FIG. 2 is a timing diagram showing the operation of the circuit for controlling the core voltage driver in the conventional semiconductor memory device illustrated in FIG. 1.
Referring to FIG. 2, the circuit for controlling the core voltage driver in the conventional semiconductor memory device including the plurality of banks 30 to 37 sequentially activates the plurality of bank selection driving control signals RACTV<0> to RACTV<7>, as a plurality of active commands ACT_CMD (ACT0 to ACT7) corresponding to the plurality of banks 30 to 37 are sequentially activated. Accordingly, the plurality of driving control pulses ENPULSE01, ENPULSE23, ENPULSE45, and ENPULSE67 are sequentially toggled to sequentially drive the core voltage terminals corresponding to the plurality of banks 30 to 37.
When the plurality of active command signals ACT0 to ACT7 corresponding to the plurality of banks 30 to 37 are sequentially activated, the read command signal READ_CMD (RD0 or RD1) for reading data stored in the 0-th or first bank (30 or 31) is applied. Accordingly, the driving control signal YBST is toggled.
When the driving control signal YBST is toggled in response to the application of the read command signal RD0 or RD1 for reading the data stored in the 0-th or first bank 30 or 31, only the pulse ENPULSE01 corresponding to the 0-th and first banks 30 and 31 among the plurality of driving control pulses ENPULSE01, ENPULSE23, ENPULSE45, and ENPULSE67 is toggled, and the other pulses ENPULSE23, ENPULSE45, and ENPULSE67 corresponding to the second to seventh banks 32 to 37 are not toggled, until the bank selection driving control signals RACTV<0> and RACTV<1> corresponding to the 0-th and first banks, 30 and 31, among the plurality of bank selection driving control signals RACTV<0> to RACTV<7> are activated. Therefore, the core voltage terminals corresponding to the 0-th and first banks (30 and 31) may be driven with optimal efficiency.
However, when the read command signal RD0 or RD1 for reading the data stored in the 0-th or first bank 30 or 31 is applied to toggle the driving control signal YBST while the bank selection driving control signals RACTV<2> to RACTV<7> corresponding to the second to seventh banks 32 to 37 among the plurality of bank selection driving control signals RACTV<0> to RACTV<7> are sequentially activated, the driving control pulses ENPULSE23, ENPULSE45, and ENPULSE67 corresponding to the second to seventh banks 32 to 37 as well as the driving control pulse ENPULSE01 corresponding to the 0-th and first banks (30 and 31) may also be toggled to drive the core voltage terminals corresponding to the second to seventh banks 32 to 37 as well as the core voltage terminals corresponding to the 0-th and first banks 30 and 31.
That is, when the read command signal RD0 or RD1 is applied to read the data stored in the 0-th or first bank (30 or 31), only the core voltage terminals of the 0-th and first banks 30 and 31 may be driven. However, the core voltage terminals of the second to seventh banks 32 to 37, which are not objects of the intended operation, may be unnecessarily driven when the second to seventh banks 32 to 37 are activated in correspondence to the active command signals ACT_CMD before the read command signal RD0 or RD1 is applied.
When the core voltage terminals of the second to seventh banks 32 to 37 are unnecessarily driven perform an operation, current consumption may increase.